The present disclosure relates to semiconductor integrated circuits used in LSI employing microfabrication process technology, in which data signals are transferred at a high transfer rate from the core of a sender to the core of a receiver.
Conventionally, in an LSI circuit, when a data signal is transferred from the core (circuit) of a sender to the core (circuit) of a receiver, a clock is supplied from the same source point to both of the sender's core and the receiver's core so that flip-flops (hereinafter referred to as “FFs”) in the sender's core and the receiver's core operate in synchronization with each other. In such an operation scheme, if the operation is performed at a clock frequency of as high as several gigahertz or higher, a data signal cannot be correctly transferred unless the total of a delay time in the FF of the sender's core, a delay time in an interconnect between the cores, and a setup time in the FF of the receiver's core is smaller than or equal to the period of one cycle of the clock.
In an effort to address this problem, a semiconductor integrated circuit has been described in which data and a source clock are simultaneously transferred from the sender's LSI in the same transmission path, and in the receiver's LSI, the data is sampled using the source clock and then synchronized with the clock of the receiver's LSI, whereby variations in the delay time of the transmission path and clock skew are reduced (see Japanese Patent Publication No. 2000-347993 (hereinafter referred to as Patent Document 1)).
However, in the conventional technique described in Patent Document 1, when data signals are transferred at high speed in the microfabrication process, it is difficult to ensure an eye pattern. For example, as the microfabrication process has been advanced, the gate lengths of transistors have been reduced, so that the lengths of interconnects for signals in blocks have also been reduced. Therefore, a fine layer used in the interconnect in the block can maintain the performance thereof even if the sheet resistance and coupling capacitance of the fine layer are high. On the other hand, the total number of hard macros and processors mounted in an LSI circuit increases, and therefore, the chip area of the LSI circuit is almost constant. As a result, the interconnect length of the transmission path is constant, and therefore, the values of a parasitic resistance and capacitance increase, so that the eye pattern becomes smaller due to the fluctuation (jitter) of data.
In an effort to address the problem with Patent Document 1, a semiconductor integrated circuit has been described in which a double edge triggered latch is used to re-adjust the skew (jitter) of data occurring when the data is transferred over a long-distance interconnect (see Blaine Stackhouse, et al., “A 65 nm 2-Billion Transistor Quad-Core Itanium Processor,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 1, pp. 18-31, JANUARY 2009 (hereinafter referred to as a Non-Patent Document 1)).
FIG. 21 shows an example double edge triggered latch. The double edge triggered latch is a circuit which, when a change (rise and fall of a waveform) occurs in the voltage level of a trigger signal CK, latches the value of a data signal D and propagates the value of the data signal D to an output Q. Note that, in FIG. 21, a reference character CKN indicates an inverted trigger signal obtained by inverting the trigger signal CK, and a reference character CKP indicates a non-inverted trigger signal obtained by inverting the inverted trigger signal CKN.
On the other hand, in the level triggered latch shown in FIG. 22, when the potential level of the trigger signal CK is at the high level, the value of the data signal D is propagated to the output Q, and when the potential level of the trigger signal CK is at the low level, the value of the output Q is maintained. Note that, in FIG. 22, a reference character CKB indicates an inverted trigger signal obtained by inverting the trigger signal CK.
The double edge triggered latch shown in FIG. 21 is different from the level triggered latch shown in FIG. 22, in that two master latches which capture data at the rise and fall of the waveform, and a slave latch which switches the master latches, i.e., selects one of them as a transfer target, at the rise and fall of the waveform, are required. Therefore, at least three stages of transistors are required in a path in which a data signal is transferred, resulting in a complicated circuit.
In other words, in the conventional technique described in Non-Patent Document 1, there is a high latency in a data signal in a long-distance interconnect which requires a plurality of double edge triggered latches for re-adjusting data skew. Also, because a single clock signal is used as a trigger signal to operate the double edge triggered latches, the power consumption increases and the level of noise becomes higher.